lager_pcb.rigol_mso5000_defines
Module Contents
Classes
Attributes
- class lager_pcb.rigol_mso5000_defines.CursorMode
Bases:
lager_pcb.visa_enum.VisaEnum
- Off = OFF
- Manual = MANual
- Track = TRACk
- XY = XY
- Measure = MEASure
- class lager_pcb.rigol_mso5000_defines.CursorType
Bases:
lager_pcb.visa_enum.VisaEnum
- Time = TIME
- Amplitude = AMPLitude
- class lager_pcb.rigol_mso5000_defines.CursorSource
Bases:
lager_pcb.visa_enum.VisaEnum
- Channel1 = CHANnel1
- Channel2 = CHANnel2
- Channel3 = CHANnel3
- Channel4 = CHANnel4
- Math1 = MATH1
- Math2 = MATH2
- Math3 = MATH3
- Math4 = MATH4
- Logic = LA
- NoSource = NONE
- class lager_pcb.rigol_mso5000_defines.CursorUnit
Bases:
lager_pcb.visa_enum.VisaEnum
- Second = SECond
- Hertz = HZ
- Degree = DEGRee
- Percent = PERCent
- class lager_pcb.rigol_mso5000_defines.ScopeChannel
Bases:
lager_pcb.visa_enum.VisaEnum
- Channel1 = 1
- Channel2 = 2
- Channel3 = 3
- Channel4 = 4
- class lager_pcb.rigol_mso5000_defines.TriggerType
Bases:
lager_pcb.visa_enum.VisaEnum
- Edge = EDGE
- Pulse = PUL
- Slope = SLOP
- Video = VID
- Pattern = PATT
- Duration = DUR
- Timeout = TIM
- Runt = RUNT
- Window = WIND
- Delay = DEL
- Setup = SET
- NEdge = NEDG
- RS232 = RS232
- IIC = IIC
- SPI = SPI
- CAN = CAN
- Flexray = FLEX
- LIN = LIN
- IIS = IIS
- M1553 = M1553
- class lager_pcb.rigol_mso5000_defines.TriggerCoupling
Bases:
lager_pcb.visa_enum.VisaEnum
- AC = AC
- DC = DC
- LF_Reject = LFR
- HF_Reject = HFR
- class lager_pcb.rigol_mso5000_defines.TriggerStatus
Bases:
lager_pcb.visa_enum.VisaEnum
- TD = TD
- WAIT = WAIT
- RUN = RUN
- AUTO = AUTO
- STOP = STOP
- class lager_pcb.rigol_mso5000_defines.TriggerMode
Bases:
lager_pcb.visa_enum.VisaEnum
- Auto = AUTO
- Normal = NORM
- Single = SING
- class lager_pcb.rigol_mso5000_defines.TriggerEdgeSource
Bases:
lager_pcb.visa_enum.VisaEnum
- D0 = D0
- D1 = D1
- D2 = D2
- D3 = D3
- D4 = D4
- D5 = D5
- D6 = D6
- D7 = D7
- D8 = D8
- D9 = D9
- D10 = D10
- D11 = D11
- D12 = D12
- D13 = D13
- D14 = D14
- D15 = D15
- Channel1 = CHAN1
- Channel2 = CHAN2
- Channel3 = CHAN3
- Channel4 = CHAN4
- AC_Line = ACL
- class lager_pcb.rigol_mso5000_defines.TriggerEdgeSlope
Bases:
lager_pcb.visa_enum.VisaEnum
- Positive = POS
- Negative = NEG
- Either = RFAL
- class lager_pcb.rigol_mso5000_defines.TriggerSlopeSource
Bases:
lager_pcb.visa_enum.VisaEnum
- Channel1 = CHAN1
- Channel2 = CHAN2
- Channel3 = CHAN3
- Channel4 = CHAN4
- class lager_pcb.rigol_mso5000_defines.TriggerSlopeCondition
Bases:
lager_pcb.visa_enum.VisaEnum
- Greater = GRE
- Less = LESS
- GLess = GLES
- class lager_pcb.rigol_mso5000_defines.TriggerSlopeWindow
Bases:
lager_pcb.visa_enum.VisaEnum
- TA = TA
- TB = TB
- TAB = TAB
- class lager_pcb.rigol_mso5000_defines.TriggerPulseSource
Bases:
lager_pcb.visa_enum.VisaEnum
- D0 = D0
- D1 = D1
- D2 = D2
- D3 = D3
- D4 = D4
- D5 = D5
- D6 = D6
- D7 = D7
- D8 = D8
- D9 = D9
- D10 = D10
- D11 = D11
- D12 = D12
- D13 = D13
- D14 = D14
- D15 = D15
- Channel1 = CHAN1
- Channel2 = CHAN2
- Channel3 = CHAN3
- Channel4 = CHAN4
- class lager_pcb.rigol_mso5000_defines.TriggerPulseCondition
Bases:
lager_pcb.visa_enum.VisaEnum
- Greater = GRE
- Less = LESS
- GLess = GLES
- class lager_pcb.rigol_mso5000_defines.MeasurementSource
Bases:
lager_pcb.visa_enum.VisaEnum
- D0 = D0
- D1 = D1
- D2 = D2
- D3 = D3
- D4 = D4
- D5 = D5
- D6 = D6
- D7 = D7
- D8 = D8
- D9 = D9
- D10 = D10
- D11 = D11
- D12 = D12
- D13 = D13
- D14 = D14
- D15 = D15
- Channel1 = CHAN1
- Channel2 = CHAN2
- Channel3 = CHAN3
- Channel4 = CHAN4
- Math1 = MATH1
- Math2 = MATH2
- Math3 = MATH3
- Math4 = MATH4
- class lager_pcb.rigol_mso5000_defines.MeasurementClear
Bases:
lager_pcb.visa_enum.VisaEnum
- Item1 = ITEM1
- Item2 = ITEM2
- Item3 = ITEM3
- Item4 = ITEM4
- Item5 = ITEM5
- Item6 = ITEM6
- Item7 = ITEM7
- Item8 = ITEM8
- Item9 = ITEM9
- Item10 = ITEM10
- All = ALL
- class lager_pcb.rigol_mso5000_defines.MeasurementItem
Bases:
lager_pcb.visa_enum.VisaEnum
- VMax = VMAX
- VMin = VMIN
- VPP = VPP
- VTop = VTOP
- VBase = VBASe
- VAmp = VAMP
- VAvg = VAVG
- VRMS = VRMS
- Overshoot = OVERshoot
- Preshoot = PREShoot
- MArea = MARea
- MPArea = MPARea
- Period = PERiod
- Frequency = FREQuency
- RTime = RTIMe
- FTime = FTIMe
- PWidth = PWIDth
- NWidth = NWIDth
- PDuty = PDUTy
- NDuty = NDUTy
- TVMax = TVMAX
- TVMin = TVMIN
- PSlewrate = PSLewrate
- NSlewrate = NSLewrate
- VUpper = VUPPer
- VMid = VMID
- VLower = VLOWer
- Variance = VARiance
- PVRMS = PVRMs
- PPulses = PPULses
- NPulses = NPULses
- PEdges = PEDGes
- NEdges = NEDGes
- RRDelay = RRDelay
- RFDelay = RFDelay
- FRDelay = FRDelay
- FFDelay = FFDelay
- RRPhase = RRPHase
- RFPhase = RFPHase
- FRPhase = FRPHase
- FFPhase = FFPHase
- class lager_pcb.rigol_mso5000_defines.WaveformFormat
Bases:
lager_pcb.visa_enum.VisaEnum
- CSV = CSV
- RAW = RAW
- class lager_pcb.rigol_mso5000_defines.MathOperator
Bases:
lager_pcb.visa_enum.VisaEnum
- Add = ADD
- Subtract = SUBTract
- Multiply = MULTiply
- Divide = DIVision
- And = AND
- Or = OR
- Xor = XOR
- Not = NOT
- FFT = FFT
- Intg = INTG
- Diff = DIFF
- Sqrt = SQRT
- Log = LOG
- Ln = LN
- Exp = EXP
- Abs = ABS
- LowPass = LPASs
- HighPass = HPASs
- BandPass = BPASs
- BandStop = BSTop
- AXB = AXB
- class lager_pcb.rigol_mso5000_defines.MathSource
Bases:
lager_pcb.visa_enum.VisaEnum
- Channel1 = CHANnel1
- Channel2 = CHANnel2
- Channel3 = CHANnel3
- Channel4 = CHANnel4
- Ref1 = REF1
- Ref2 = REF2
- Ref3 = REF3
- Ref4 = REF4
- Ref5 = REF5
- Ref6 = REF6
- Ref7 = REF7
- Ref8 = REF8
- Ref9 = REF9
- Ref10 = REF10
- Math1 = MATH1
- Math2 = MATH2
- Math3 = MATH3
- lager_pcb.rigol_mso5000_defines.MATHSOURCE_TO_CHANNEL
- class lager_pcb.rigol_mso5000_defines.MathLogicSource
Bases:
lager_pcb.visa_enum.VisaEnum
- D0 = D0
- D1 = D1
- D2 = D2
- D3 = D3
- D4 = D4
- D5 = D5
- D6 = D6
- D7 = D7
- D8 = D8
- D9 = D9
- D10 = D10
- D11 = D11
- D12 = D12
- D13 = D13
- D14 = D14
- D15 = D15
- Channel1 = CHAN1
- Channel2 = CHAN2
- Channel3 = CHAN3
- Channel4 = CHAN4
- class lager_pcb.rigol_mso5000_defines.LogicChannel
Bases:
lager_pcb.visa_enum.VisaEnum
- D0 = D0
- D1 = D1
- D2 = D2
- D3 = D3
- D4 = D4
- D5 = D5
- D6 = D6
- D7 = D7
- D8 = D8
- D9 = D9
- D10 = D10
- D11 = D11
- D12 = D12
- D13 = D13
- D14 = D14
- D15 = D15
- NoChannel = NONE
- class lager_pcb.rigol_mso5000_defines.LogicGroup
Bases:
lager_pcb.visa_enum.VisaEnum
- Group1 = GROup1
- Group2 = GROup2
- Group3 = GROup3
- Group4 = GROup4
- class lager_pcb.rigol_mso5000_defines.LogicDisplaySize
Bases:
lager_pcb.visa_enum.VisaEnum
- Small = ['SMALl', 'SMAL']
- Medium = ['LARGe', 'LARG']
- Large = ['MEDium', 'MED']
- class lager_pcb.rigol_mso5000_defines.LogicPod
Bases:
lager_pcb.visa_enum.VisaEnum
- Pod1 = POD1
- Pod2 = POD2
- class lager_pcb.rigol_mso5000_defines.BusMode
Bases:
lager_pcb.visa_enum.VisaEnum
- Parallel = PARallel
- RS232 = RS232
- SPI = SPI
- I2C = IIC
- I2S = IIS
- LIN = LIN
- CAN = CAN
- FlexRay = FLEXray
- M1553 = M1553
- class lager_pcb.rigol_mso5000_defines.BusFormat
Bases:
lager_pcb.visa_enum.VisaEnum
- Hex = HEX
- ASCII = ASCii
- Decimal = DEC
- Binary = BIN
- class lager_pcb.rigol_mso5000_defines.BusView
Bases:
lager_pcb.visa_enum.VisaEnum
- Packets = PACKets
- Details = DETails
- Payload = PAYLoad
- class lager_pcb.rigol_mso5000_defines.BusType
Bases:
lager_pcb.visa_enum.VisaEnum
- PAL = PAL
- TX = TX
- RX = RX
- SCL = SCL
- SDA = SDA
- CS = CS
- CLK = CLK
- MISO = MISO
- MOSI = MOSI
- LIN = LIN
- CAN = CAN
- CANSub1 = CANSub1
- FLEX = FLEX
- OneFiveFiveThree = 1553
- class lager_pcb.rigol_mso5000_defines.BusLogicSource
Bases:
lager_pcb.visa_enum.VisaEnum
- D0 = D0
- D1 = D1
- D2 = D2
- D3 = D3
- D4 = D4
- D5 = D5
- D6 = D6
- D7 = D7
- D8 = D8
- D9 = D9
- D10 = D10
- D11 = D11
- D12 = D12
- D13 = D13
- D14 = D14
- D15 = D15
- Channel1 = CHAN1
- Channel2 = CHAN2
- Channel3 = CHAN3
- Channel4 = CHAN4
- Off = OFF
- class lager_pcb.rigol_mso5000_defines.BusEndianness
Bases:
lager_pcb.visa_enum.VisaEnum
- MSB = MSB
- LSB = LSB
- class lager_pcb.rigol_mso5000_defines.BusUARTPolarity
Bases:
lager_pcb.visa_enum.VisaEnum
- Positive = POSitive
- Negative = NEGative
- class lager_pcb.rigol_mso5000_defines.BusUARTParity
Bases:
lager_pcb.visa_enum.VisaEnum
- NoParity = NONE
- Even = EVEN
- Odd = ODD
- class lager_pcb.rigol_mso5000_defines.BusUartPacketEnd
Bases:
lager_pcb.visa_enum.VisaEnum
- NULL = NULL
- LF = LF
- CR = CR
- SP = SP
- class lager_pcb.rigol_mso5000_defines.BusI2CAddressMode
Bases:
lager_pcb.visa_enum.VisaEnum
- Normal = NORMal
- RW = RW
- class lager_pcb.rigol_mso5000_defines.BusSPISCLSlope
Bases:
lager_pcb.visa_enum.VisaEnum
- Positive = POSitive
- Negative = NEGative
- class lager_pcb.rigol_mso5000_defines.BusSPIPolarity
Bases:
lager_pcb.visa_enum.VisaEnum
- High = HIGH
- Low = LOW
- class lager_pcb.rigol_mso5000_defines.BusSPIMode
Bases:
lager_pcb.visa_enum.VisaEnum
- CS = CS
- Timeout = TIMeout
- class lager_pcb.rigol_mso5000_defines.BusCANSigType
Bases:
lager_pcb.visa_enum.VisaEnum
- TX = TX
- RX = RX
- CANHigh = CANH
- CANLow = CANL
- Differential = DIFFerential
- class lager_pcb.rigol_mso5000_defines.BusFlexRaySigType
Bases:
lager_pcb.visa_enum.VisaEnum
- BP = BP
- BM = BM
- RT = RT